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-- SubModule relay
-- Created   2022-1-15 21:15:46
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library IEEE;
use IEEE.Std_Logic_1164.all;

entity relay is port
   (
     VCC : inout std_logic;
     GND : inout std_logic
   );
end relay;
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architecture Structure of relay is

-- Component Declarations

-- Signal Declarations

begin

end Structure;
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